VHDL을 이용한 7세그먼트 실험보고서

소개글

VHDL을 이용한 7세그먼트 실험보고서에 대한 보고서 자료입니다.

목차

1. 7세그먼트 (숫자표시)
< 시뮬레이션 결과 >
< H/W 확인 >
< .ucf 파일 생성 >
< 동작 확인 >

1. 7세그먼트 (알파벳표시)
< 시뮬레이션 결과 >
< H/W 확인 >
< .ucf 파일 생성 >
< 동작 확인 >

본문내용

0000000010000000\" => Segout7 <= \"1111111\"; --8
when \"0000000100000000\" => Segout7 <= \"1111011\"; --9
when \"0000001000000000\" => Segout7 <= \"1111110\"; --0
when \"0000010000000000\" => Segout7 <= \"1110111\"; --A
when \"0000100000000000\" => Segout7 <= \"0011111\"; --B
when \"0001000000000000\" => Segout7 <= \"0001101\"; --C
when \"0010000000000000\" => Segout7 <= \"0111101\"; --D
when \"0100000000000000\" => Segout7 <= \"1001111\"; --E
when \"1000000000000000\" => Segout7 <= \"1000111\"; --F
when others => Segout7 <= \"ZZZZZZZ\";
end case;
end if;
end process;
end Behavioral;
< 시뮬레이션 결과 >
< H/W 확인 >
begin
EN <= \'1\' X <=\"0000000000000001\"; Wait for 100ns;
EN <= \'1\' X <=\"0000000000000010\"; Wait for 100ns;
EN <= \'1\' X <=\"0000000000000100\"; Wait for 100ns;
EN <= \'1\' X <=\"0000000000001000\"; Wait for 100ns;
EN <= \'1\' X <=\"0000000000010000\"; Wait for 100ns;
EN <= \'1\' X <=\"0000000000100000\"; Wait for 100ns;
EN <= \'1\' X <=\"0000000001000000\"; Wait for 100ns;
EN <= \'1\' X <=\"0000000010000000\"; Wait for 100ns;
EN <= \'1\' X <=\"0000000100000000\"; Wait for 100ns;
EN <= \'1\' X <=\"0000001000000000\"; Wait for 100ns;
EN <= \'1\' X <=\"0000010000000000\"; Wait for 100ns;
EN <= \'1\' X <=\"0000100000000000\"; Wait for 100ns;
EN <= \'1\' X <=\"0001000000000000\"; Wait for 100ns;
EN <= \'1\' X <=\"0010000000000000\"; Wait for 100ns;
EN <= \'1\' X <=\"0100000000000000\"; Wait for 100ns;
EN <= \'1\' X <=\"1000000000000000\"; Wait for 100ns;
EN <= \'0\' X <=\"0000000000000001\"; Wait for 100ns;
EN <= \'0\' X <=\"0000000000000010\"; Wait for 100ns;
EN <= \'0\' X <=\"0000000000000100\"; Wait for 100ns;
EN <= \'0\' X <=\"0000000000001000\"; Wait for 100ns;
EN <= \'0\' X <=\"0000000000010000\"; Wait for 100ns;
EN <= \'0\' X <=\"0000000000100000\"; Wait for 100ns;
EN <= \'0\' X <=\"0000000001000000\"; Wait for 100ns;
EN <= \'0\' X <=\"0000000010000000\"; Wait for 100ns;
EN <= \'0\' X <=\"0000000100000000\"; Wait for 100ns;
EN <= \'0\' X <=\"0000001000000000\"; Wait for 100ns;
EN <= \'0\' X <=\"0000010000000000\"; Wait for 100ns;
EN <= \'0\' X <=\"0000100000000000\"; Wait for 100ns;
EN <= \'0\' X <=\"0001000000000000\"; Wait for 100ns;
EN <= \'0\' X <=\"0010000000000000\"; Wait for 100ns;
EN <= \'0\' X <=\"0100000000000000\"; Wait for 100ns;
EN <= \'0\' X <=\"1000000000000000\"; Wait for 100ns;
end process;
END;
< .ucf 파일 생성 >
NET EN LOC = P41;
NET \"X<15>\" LOC = P42;
NET \"X<14>\" LOC = P43;
NET \"X<13>\" LOC = P44;
NET \"X<12>\" LOC = P45;
NET \"X<11>\" LOC = P46;
NET \"X<10>\" LOC = P47;
NET \"X<9>\" LOC = P48;
NET \"X<8>\" LOC = P49;
NET \"X<7>\" LOC = P57;
NET \"X<6>\" LOC = P58;
NET \"X<5>\" LOC = P59;
NET \"X<4>\" LOC = P60;
NET \"X<3>\" LOC = P61;
NET \"X<2>\" LOC = P62;
NET \"X<1>\" LOC = P63;
NET \"X<0>\" LOC = P67;
NET \"Segout<6>\" LOC = P127;
NET \"Segout<5>\" LOC = P126;
NET \"Segout<4>\" LOC = P125;
NET \"Segout<3>\" LOC = P123;
NET \"Segout<2>\" LOC = P122;
NET \"Segout<1>\" LOC = P121;
NET \"Segout<0>\" LOC = P120;
NET \"com<7>\" LOC = P115;
NET \"com<6>\" LOC = P114;
NET \"com<5>\" LOC = P113;
NET \"com<4>\" LOC = P112;
NET \"com<3>\" LOC = P111;
NET \"com<2>\" LOC = P110;
NET \"com<1>\" LOC = P109;
NET \"com<0>\" LOC = P108;
< 동작 확인 >

키워드

VHDL,   실험보고서,   7세그먼트,   Seven Segment