|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity data_gen is
port(reset, active : in std_logic;
V_sync, Left_But, Right_But : in std_logic;
H_count, V_count : in std_logic_vector(9 downto 0);
addr : out std_logic_vector(
|
|
메뉴펼치기
