성균관대학교 디지털집적회로설계 CAD 첫번째 과제

소개글

성균관대학교 디지털집적회로설계 CAD 첫번째 과제에 대한 보고서 자료입니다.

목차

1. (DC Simulation) Simulate the voltage transfer characteristic of CMOS inverter with varying (WpWn) ratio from 1 to 5. (Fix Wn = 1μm and sweep Wp from 1μm to 5μm (Step size = 0.5μm) using [Tools]-[Parametric Analysis] in ADE L window). Find the optimum (WpWn) ratio where the logical threshold voltage is half of VDD and describe the reason. Attach screenshots for optimal VTC and ID number like below. (Simulate at NN corner)
2. (DC Simulation) Using optimum CMOS inverter derived from 1, derive voltage transfer curve for different process corners (NN, FF, SS, FS, and SF) and explain differences of each corner’s result (You can switch process corner condition with “Section” tap in [Setup] – [Model Libraries] menu in ADE L window.) Attach screenshots for FS and SF corners.
3. (Transient Simulation) Assume an inverter is driving a 500 fF load capacitor and total width of PMOS and NMOS is 3μm (Wn + Wp= 3μm). Find optimum (Wn/Wp) ratio of CMOS inverter to
(1) minimize propagation delay
(2) give balanced tpHL and tpLH.
Use input signal as pulse with 10 ns period, and rising/falling time of 20 ps. Which optimum ratio is close to the result from DC simulation in problem 1? Explain the reason.
4. (Transient Simulation) Design a ring oscillator using 7 inverters. Assuming the total width of PMOS and NMOS of each inverter is 3μm (Wn + Wp= 3μm), Sweep Wn from 0.3μ to 2.7μ.
(Step size = 0.3μ)
(Don’t forget to set the initial condition for one node!)
(1) Plot tpLH, tpHL, and period.
A. Explain why you get the results.
B. If tpHL was lower than zero, explain how it could be possible.
(2) Figure out the ways to make the period longer, means longer delay

본문내용

성균관대학교 디지털집적회로설계 CAD 첫번째 과제

소개글
성균관대학교 디지털집적회로설계 과목 CAD 과제입니다. (학점은 A입니다)
꼭 과제를 위해서가 아니더라도, CAD 실습 과제의 주제가 반도체 쪽 실무적인 관점에서
공부를 하기에 좋은 자료이니 목차
참고하시고 필요하신 내용이 있다면 참고하시면 좋을것 같아요! ^^
목차
1. (DC Simulation) Simulate the voltage transfer characteristic of CMOS inverter with varying (WpWn) ratio from 1 to 5. (Fix Wn = 1μm and sweep Wp from 1μm to 5μm (Step size = 0.5μm) using [Tools]-[Parametric Analysis] in ADE L window). Find the optimum (WpWn) ratio where the logical threshold voltage is half

키워드

레포트,   학점은행제,   평생교육원,   과제,   방송통신대,   방통대,   학은제